Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

An analysis of the efficiency of power-gating for clock storage elements (CSE) is presented. Two CSE topologies: the TGMS (Transmission Gate Master Slave) and the WPMS (Write Port Master Slave) are examined along with their respective circuits with sleep transistors. In this work, we study the benefits of adding sleep transistors coupled with regular clock-gating during inactive mode. We examine the energy savings for standard clock gated CSEs versus their power gated counterparts. This is done by studying how the leakage energy saved with power gating offsets the energy consumed by the extra transistors added to support it. It is not always beneficial to add sleep transistors when deciding between power-gating or just using clock-gating. We also study how the results and tradeoff change with voltage scaling.